1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, particularly to a technology which is effective by being applied to a semiconductor integrated circuit having a plurality of semiconductor chips.
Further, the present invention relates to a semiconductor integrated circuit, particularly to a technology which is effective by being applied to a test of a semiconductor integrated circuit of SIP (System In Package) mounting a plurality of semiconductor chips on a single package.
2. Description of the Related Art
According to a multichip package (semiconductor integrated circuit) having a plurality of semiconductor elements (semiconductor chip) of a related art, a portion of a lead is extended from one side edge side to other side edge side without being brought into contact with a main face of at least one semiconductor element to thereby intersect the lead and the semiconductor element three-dimensionally and inner electrodes of the plurality of semiconductor elements are connected to a common lead by bonding wires (refer to, for example, Patent Reference 1).
Further, in a test of a semiconductor integrated circuit of SIP, it is necessary to carry out a leakage test of input/output terminals of a plurality of semiconductor chips (hereinafter, also referred to simply as “chip”) mounted to, for example, SIP also for a terminal which does not output to outside of SIP. Hence, in a related art, in order to ensure performance of facilitating a test after having been integrated, all of terminals connecting the chips mounted to SIP are extruded to outside of SIP.
Further, there is a technology described in Patent Reference 2 as means for testing a memory in SIP including CPU and the memory. Further, there is a technology described in Patent Reference 3 as means for detecting a leakage current in noncontact for input/output terminals.    (Patent Reference 1) JP-A-6-151685 (FIG. 1)    (Patent Reference 2) JP-A-9-160802    (Patent Reference 3) JP-A-10-123212
There is known a semiconductor integrated circuit referred to as SIP including a semiconductor chip (hereinafter, also referred to as microcomputer chip) having a processing function and a semiconductor chip (hereinafter, also referred to as memory chip) having a memory circuit.
Although the main stream is constituted by SIP of a substrate type in view of a high degree of freedom of leading around wirings, the substrate type is accompanied by high cost.
Hence, the inventors have investigated on SIP of a frame type integrated by using a lead frame for reducing cost. As a result, there has been found a problem that in a multipins constitution, a semiconductor integrated circuit becomes more large-sized than in the substrate type.
Further, although Patent Reference 1 (JP-A-6-151685), mentioned above, describes a multichip package of a frame type, a technology of achieving small-sized formation of a semiconductor integrated circuit of a multipin type is not described.
Further, as a result of investigating a technology of testing semiconductor integrated circuit of SIP by the inventors, the following becomes apparent.
For example, according to an SIP product, also a terminal connecting chip which is not necessary for a customer is excluded to outside of the SIP in view of performance of facilitating a test after having been integrated and therefore, a number of terminals (pins) is increased and a package size tends to increase.